Software Darwinism 3.0
The EDA Software Market: The Ultimate Software Moat Against AI Disruption
This third and final installment of the Software Darwinism series won’t focus on CSU or its spin-offs. I’ve written extensively about them over the last four or five months (don’t worry, there will be more coming), but this piece takes a different direction entirely.
If you’d like to read the first two parts before diving in, here are the links:
🔗 Software Darwinism: Does All SaaS Die in the Age of AI? And Where Does Constellation Software Fit?
This third piece is heavily influenced by the SemiAnalysis EDA market primer launched a few weeks ago, which I’d encourage every reader to go through in full. Here is the link: 🔗 EDA Market Primer - Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise
The core argument they lay out is one I find compelling and, frankly, underappreciated by most investors when assessing software and their moats: Electronic Design Automation (EDA) at the leading edge is the closest thing to a true utility monopoly that exists in the entire technology stack … and it happens to be software.
Weird, isn’it?
While nearly every software vendor faces some narrative of AI-driven disruption, EDA, dominated by the duopoly of Synopsys and Cadence, operates in a structurally different category. You cannot design a microchip, an AI accelerator, or an advanced system-on-chip without their IP and physics-based software suites. These tools are not just optional productivity layers, they are engineering constraints embedded directly into the semiconductor and systems development process.
That’s precisely what makes them so valuable.
The Three-Headed Moat
The competitive moats here are self-reinforcing in a way that’s very rare to find, even among the best vertical software businesses.
The first and most obvious moat is switching costs, but I’d argue the market still underestimates just how punishing they are in practice. A chip design team spends years mastering the proprietary tool chains embedded in either Cadence’s or Synopsys’s ecosystems. Forcing hundreds of highly specialized engineers off tools like Virtuoso (Cadence) or Design Compiler (Synopsys) onto an unproven alternative delays time-to-market by years and introduces risk of catastrophic tape-out failure. A tape-out failure on a leading-edge chip can cost hundreds of millions of dollars and set a product roadmap back an entire generation. No CFO is signing off on that risk to save on an EDA license that makes up a small portion of their R&D spend.
The second moat is less talked about and, in my view, the most underappreciated of the three. For an EDA tool to be usable at the leading edge, it must be rigorously calibrated to the physical manufacturing capabilities of the foundry it’s targeting. TSMC, Intel Foundry, and Samsung provide confidential, hyper-precise Process Design Kits (PDKs) exclusively to Synopsys and Cadence, and they do so years before a new manufacturing node goes live. This isn’t a business arrangement that a new entrant can negotiate its way into. The data required to write competitive EDA software for leading-edge nodes is, quite literally, inaccessible to everyone else.
The third moat is what I’d call the “Lego Brick” lock-in. Chip designers don’t build chips from scratch; they license pre-designed building blocks (PCIe interfaces, DDR controllers, memory PHYs, etc.) and drop them into their layouts. Synopsys and Cadence are the world’s dominant suppliers of this non-processor physical IP. Because their software tools are natively optimized to integrate these IP blocks seamlessly, customers face compounding switching costs: leaving the software ecosystem also means leaving the IP ecosystem. The two reinforce each other in a closed loop that makes migration not just painful but economically irrational.
Put all three together and you have one of the most structurally defensible business models in technology: extreme switching costs, gated access to foundry data, and deeply embedded IP blocks. A legacy software competitor starting from scratch is just very unlikely to succeed.
The AI Opportunity
Historically, EDA was a software tool wielded by human engineers. Generative AI is fundamentally restructuring that relationship, and I think most investors (and I include myself) are still sleeping on what this means for the pricing power and TAM of CDNS and SNPS over the next decade.
Designing a chip layout involves navigating an astronomical number of physical variables to balance what engineers call PPA: Power, Performance, and Area. Traditionally, a human engineer might spend weeks manually tweaking these variables to find an acceptable solution. Tools like Synopsys’s DSO.ai and Cadence’s Cerebrus use reinforcement learning to autonomously discover near-optimal layouts in days, consistently delivering double-digit power savings and dramatically shorter time-to-market. This becomes a step-change in what their software can do.
Here’s Anirudh Devgan (Cadence’s CEO) during Q1 2026 conference when asked about AI’s multiplier effect on Core EDA usage:
“When a user designs a chip... 1 engineer will run like 1 or 2 experiments. But when the agent runs those blocks, they may try 10 or 100 variations of those things... So not only agent can give more productivity, it by nature runs more of the base tools.” — Anirudh Devgan, CEO
What’s interesting about this shift is the pricing implication and how Cadence and Synopsys are already benefitting from it.
Once an EDA tool demonstrably saves a customer $50 million in engineering labor, wafer space, and several months of development time, the historical “per-seat software license” model starts to look materially underpriced.
Even activist investor Elliott Investment Management (now influential at Synopsys following its large stake) has called out this dynamic, arguing that EDA vendors likely have far more pricing power than the market appreciates.
What’s emerging instead is a hybrid “subscription + consumption” model, and the effects are already beginning to flow through revenue growth and margins. Cadence management was unusually explicit about this during the Q1 2026 earnings call.
On agentic AI and the transition toward consumption-based pricing, CEO Anirudh Devgan stated:
“What agentic AI allows us is to sell products in spaces we didn’t have products before, like RTL generation and analog automation... So that will be priced as a subscription plus consumption model, very similar to other kind of leading AI tools. So that’s a completely new category for Cadence... And then in turn, agentic AI will drive more of our base tools.”
Meanwhile, CFO John Wall highlighted the operating leverage embedded in the model:
“When we look at our organic incremental margin, it’s closer to 60% these days than 50%... With the benefits that we’re seeing in terms of customer engagement accelerating on the agentic AI front, I think there’s even more opportunities to stretch that incremental operating margin going forward.”
The implication is significant: both Cadence and Synopsys may be entering a phase where AI not only reinforces their moats, but also structurally expands monetization and margins.
That likely explains why these stocks have continued to rerate upward while much of the broader software universe still struggles with AI disruption fears.
There’s also another angle here that I find particularly interesting: the hyperscaler in-sourcing tailwind. As Google, Amazon, and Meta aggressively pivot toward designing custom internal ASICs (TPUs, Inferentia, MTIA) they are simultaneously trying to execute these designs with lean hardware teams. They lack the deep armies of hardware specialist engineers that traditional semiconductor companies have built over decades The solution, not coincidentally, is to lean heavily on the AI-automated design suites of CDNS and SNPS. The hyperscaler arms race to reduce NVIDIA dependency is not a headwind for EDA. It is a recurring, structural cash tailwind.
And this is actually where I’ve changed my mind. Previously, I held a more bearish view around the risk of hyperscalers eventually developing internal EDA capabilities. But the deeper I’ve dug into the complexity, physics constraints, and embedded workflows of modern chip design, the less likely that outcome appears (at least at scale).
I’ll dedicate an entire section to this topic at the end of this piece for Expanse Stocks subscribers.
The Risks of AI Disruption
The bearish scenario that’s been more discussed is the in-house AI challenge. If a tech giant with massive computational scale (say, NVIDIA) were to build a proprietary, highly specialized AI model capable of autonomously routing and verifying circuits better than the broad generalized models built by Cadence or Synopsys, you could make the case that dependency on legacy EDA suites declines over time. Google’s AlphaChip work has been the most visible example of this ambition. I don’t want to dismiss the possibility entirely, but I think the SemiAnalysis framework makes a fairly convincing case for why the incentives to pursue this aren’t as strong as they appear. (I’ll get into this more in detail in the last section reserved for subscribers.)
The second risk is Synopsys-specific and more near-term. Synopsys has finalized its multi-billion $ acquisition of Ansys, a leader in engineering simulation software. The strategic logic is sound: modern chips are stacked vertically in 3D-IC configurations and face extreme thermal and structural stress, so combining electronic design with physical simulation creates an extraordinarily deep, full-stack workflow moat. But the execution risk is real. This is a large, complex integration that stretches Synopsys’s balance sheet and creates a multi-year vulnerability that Cadence doesn’t have to worry about. I think of this less as a structural threat to the thesis and more as a company-specific risk that will make SNPS noisier to own over the next two to three years.
Structural Growth Outlook: Decoupled From the Cycle
One of the things I find most compelling about the EDA business model is its decoupling from the consumer electronics cycle that tends to drag down sentiment on anything with “semiconductor” in the description. EDA revenue scales with the volume of R&D chip design starts, not with the physical volume of manufacturing units shipped. Every time a car manufacturer designs a custom EV chip, a medical device company develops an embedded IoT sensor, or a tech giant refreshes its AI accelerator architecture, they must pay the EDA tax.
This means that even in a world where smartphone and PC sales flatline, EDA compounds because the underlying driver, i.e. the proliferation of custom silicon and embedded complex systems across every industry vertical, is secular, not cyclical. The market is essentially paying for an annuity on the complexity of the modern world.
I’d argue that’s one of the highest-quality growth profiles in the entire technology stack, and it’s one that remains durable precisely because of the moats discussed above.